Memory devices with page buffer having dual registers and method of using the same

ABSTRACT

A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 11/153,638, filed Jun. 14, 2005, now pending, which is a continuation of U.S. patent application Ser. No. 10/315,897, filed Dec. 9, 2002, now pending, which is a continuation-in-part of U.S. patent application Ser. No. 10/013,191, filed Dec. 7, 2001, now issued U.S. Pat. No. 6,671,204, which claims priority from U.S. Provisional Application No. 60/307,572, filed Jul. 23, 2001, all of which are hereby incorporated by reference in their entirety.

BACKGROUND

1. Technical Field

This disclosure relates to the field of semiconductor memory devices and, more specifically, to a flash memory device with a page buffer circuit having dual registers.

2. Description of the Related Art

The recent trends in semiconductor memory devices are for high integration, large capacity, and to support systems operating at high speeds. These trends are for both volatile memories (e.g., DRAM and SRAM) and non-volatile memories (e.g., flash memories).

Flash memories are generally subdivided into NOR-type flash memories and NAND-type flash memories. The NOR-type flash memories are used in applications necessary for reading information of a low volume at a high speed non-sequentially, while the NAND-type flash memories are used in applications necessary for reading information sequentially.

Flash memory devices use memory cells to store data. The memory cells include cell transistors. Each cell transistor has a control electrode and a floating gate. Since the flash memory device stores information using tunneling via an insulation film, it takes some time to store information.

In order to store information of a large volume in a short time, the NAND-type flash memory uses a register, which is also known as a page buffer circuit. Large volumes of data are supplied externally, for quick storing in the storage region. They are first stored in the register, and from there in the memory cells.

In the case of a conventional NAND-type flash memory, the magnitude of a page of data does not exceed 512 bytes. If it is assumed that a program time (or information storing time) of a NAND-type flash memory is about 200 to 500 microseconds, and 1-byte of data is loaded on the page buffer circuit from the exterior in a period of 100 nanoseconds, it takes about 50 microseconds to load 512-byte information in the page buffer circuit.

FIG. 1 shows a specific example in the prior art. FIG. 1 of the instant document is from U.S. Pat. No. 5,831,900 (that document's FIG. 7). Additional reference numerals have been added for the present discussion.

The device of FIG. 1 teaches that data are loaded to a latch 30 from a data line IO, after page buffers 20-i are reset by the surrounding circuitry. The data loaded to the latch are programmed to the memory cells 2-1, 2-2, 2-3, through a transistor Q4 (often by receiving an appropriate program command signal). This programming procedure is normally used to program NAND flash memories.

This procedure, however, has a limitation. In this program operation, if data is to be loaded to latch 30, it will have to wait until the data that was previously loaded finish programming in the previous program cycle. As it was described above, data loading to latch 30 progresses by byte units (e.g. 8 bit). So, it takes a long time for data to load to a page of as many as 2048 bytes. This is because latch 30 continues to store data until the information of the register is stored in the appropriate corresponding memory cells.

Another problem in the prior art is the copy back problem. Sometimes, a copy operation needs to be performed from a first page to a second page of data. If it is desired to perform the copy operation after the data of the memory cells in first page is latched to the latch circuit 30 through transistor Q7, then the latched data is programmed to the second page through the transistor Q4. In that case, programmed data copied to the second page are reversed, because of the latch circuit. In other words, 1 has become 0, and 0 has become 1. This problem is addressed in the prior art by providing flag cells to the memory cell array, and updating their value depending on whether the data has been inverted or not.

FIG. 2 shows a specific example of this problem in the prior art. FIG. 2 of the present document is from U.S. Pat. No. 5,996,041 (that document's FIG. 8 and FIG. 9). Additional reference numerals have been added for the present discussion.

In FIG. 2, copy back functions are shown. Data in the first page within the memory cell array is loaded to a page buffer. After that, the data is copied to another place in the array, but in inverted form. The bit to the right is the flag cell, to indicate that this data is in inverted form.

The prior art is limited as to how large the memory devices can become. For example, if it is assumed that the page buffer circuit can temporarily store 2048-byte information, it takes about 200 microseconds to load the 2048-byte of information when 1-byte information is loaded on a page buffer circuit by a period of 100 nanoseconds. Therefore the loading time is nearly similar to the information-storing time (or the program time) of 200 to 500 microseconds. Accordingly, the information-storing characteristic of the NAND-type flash memory is seriously affected by the loading time.

As integration of NAND-type flash memory increases, data must be processed in larger and larger volumes, as compared to the conventional flash memory. And it must be processed without deterioration in the information-storing characteristic.

The parent application's disclosure is briefly summarized in FIGS. 22 and 23 of the present application. As shown in FIGS. 22 and 23, a page buffer includes two registers including latches. The first register has a first latch LATCH 1 and the second register has a second latch LATCH 2. The detailed description of this structure is explained in parent U.S. patent application Ser. No. 10/013191. As shown in FIG. 22, data to be programmed is loaded to the node N4 in LATCH 1 via the Data Line during phase F1. Next the data is transferred (or dumped) from mode N4 in LATCH 1 to the node N3 of the LATCH 2 during phase F2. According to the data state of the node N3, the data is programmed to the first page of the memory cell array, during a program phase F3 in FIG. 23. If the data of the node N3 is “0” (ground level and program state), then the memory cells are programmed. If on the other hand the data of the node N3 is “1” (Vcc level and program inhibit state), then the memory cells are not programmed. Note that a page includes a group of memory cells that are controlled by one word line.

After programming, the memory cells of the page must be checked to determine whether the memory cells have been successfully programmed. This checking procedure is referred to herein as “program, verify read”, phase F4 of FIG. 23. In the program verify read procedure, if the cell to be programmed is not programmed, the state of node N3 is reset to “0” and if the cell to be programmed is programmed, the state of node N3 is reset to “1”. The cells that are not programmed must be reprogrammed according to the above program procedure.

If all of the cells are programmed, the node N3 is set to “1” during phase F5. This concludes the procedure for the first page of the memory cell array.

During the program procedure of the first page of the memory cell array, the data of the second page are simultaneously loaded to the node N4 in the LATCH 1. As a result, two procedures are carried out concurrently in a given page buffer.

U.S. Pat. No. 6,031,760 entitled SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME describes in connection with FIG. 5 thereof a prior art single-latch memory device that is typical of conventional memory devices. The described circuit has a single sense amplifier S/A that includes only a single latch circuit LT.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a memory device having a page buffer in the prior art.

FIG. 2 is an illustration of a copyback operation in the prior art, and of the flag bit it render necessary because it inverts the data.

FIG. 3 is a block diagram of a semiconductor memory device made according to an embodiment of the invention.

FIG. 4 is a diagram of an array scheme of the memory of FIG. 3.

FIG. 5 is a detailed circuit diagram of a page register and a Y-gating circuit of the device of FIG. 3.

FIG. 6 is a flowchart illustrating a programming method according to an embodiment of the present invention.

FIG. 7 is a timing diagram of signal commands for effectuating the method of FIG. 6.

FIG. 8 is a depiction of flow of data in the circuit of FIG. 5, while the signal commands of FIG. 7 are being applied.

FIG. 9 is a timing diagram of signal commands for effectuating a reading method in the device of FIG. 3.

FIG. 10 is a depiction of flow of data in the circuit of FIG. 5, while the signal commands of FIG. 9 are being applied.

FIG. 11 is a flowchart illustrating a copyback method according to an embodiment of the present invention.

FIG. 12 is a timing diagram of signal commands for effectuating a copyback method according to an embodiment of the present invention in the device of FIG. 3.

FIG. 13 is a depiction of data having been transferred from memory cells into a page buffer by following signal commands of a first portion of FIG. 12.

FIG. 14 is a depiction of data having been transferred from a page buffer into memory cells by following signal commands of a second portion of FIG. 12.

FIG. 15 is a flowchart illustrating an erase method according to an embodiment of the present invention.

FIG. 16 is a timing diagram of signal commands for effectuating an erase method in the device of FIG. 3.

FIG. 17 is a depiction of flow of data in the circuit of FIG. 5, while the signal commands of FIG. 16 are being applied.

FIG. 18 is a depiction of how large volumes of memory are counted for two alternate memory device designs.

FIG. 19 is a table illustrating various design choices for memory devices, including the two of FIG. 18.

FIG. 20 is a block diagram illustrating the arrangement of 1 block.

FIG. 21 is a diagram illustrating a time sequence of how data would be loaded according to the present invention to achieve higher capacity.

FIG. 22 is a schematic circuit diagram representing a simplified summary of the dual-register memory device described in detail in the parent application of which the present invention is a continuation in part.

FIG. 23 is a flowchart representing a simplified summary of the method for dual-register memory device programming described in detail in the parent application.

FIG. 24 is a schematic circuit diagram of a typical memory device illustrating the problem addressed by the present invention.

FIG. 25 is a graph of the distribution of voltages over a plurality of memory cells, and illustrates a problem addressed by the present invention.

FIG. 26 is a schematic circuit diagram of the invented dual-register memory device in accordance with one embodiment of the invention.

FIG. 27 is a flowchart illustrating one embodiment of the invented dual-register memory device programming method.

FIG. 28 is a timing diagram illustrating various signals and their relative timing in accordance with the invented programming method.

FIG. 29 is a graph of the distribution of voltages over a plurality of memory cells, and illustrates the solution proposed by the present invention.

DETAILED DESCRIPTION

As has been mentioned, the present invention provides semiconductor memory devices, and methods of using the same. The invention is now described in more detail.

Referring now to FIG. 3, a memory device 100 made according to the invention is described. Memory device 100 may be a NAND flash memory. Memory device 100 has an array 110 of memory cells to store data, a Page Register and Sense Amplifier (S/A) block 120, and a Y-gating circuit 130 to gate data stored in a group of the memory cells. Page Register and S/A block 120 is coupled between memory cell array 110 and Y-gating circuit 130.

Page Register and S/A block 120 includes a page buffer 122. Page buffer 122 includes dual registers according to the invention, as will be described in more detail below.

Device 100 also includes additional components, such as X-buffers latches and decoders, Y-buffers latches and decoders, a command register, a Control Logic and High Voltage Generator, and global buffers. They exchange data, address, and command signals as shown, and as will be understood from the description below.

Referring now to FIG. 4, a sample arrangement is shown for the array 110 of the memory cells. Many bit lines are shown, alternatingly designated BLe, BLo, with “e” representing even and “o” representing odd. Many memory cells (M1, M2, . . . , Mm) are connected to each bit line.

A group of memory cells (e.g. M1) are controlled by a single word line (e.g. WL1). The cells in that group are called a page unit for purposes of this application.

Referring now to FIG. 5, Page Register and S/A block 120 and Y-gating circuit 130 are described in more detail.

Y-gating circuit 130 is between Page Register and S/A block 120 and a data line 131. Data line 131 may be for bits D0-D7.

Y-gating circuit 130 is made from two NMOS transistors 132 and 133. Transistors 132 and 133 are controlled by signals YA, YB. Signals YA, YB may be derived from information from a column address.

Page Register and S/A block 120 includes a single page buffer 122, which has a sense line 125 that includes a sense node E. One or more bit lines may be connected to page buffer 122 at node E. In the example of FIG. 5, two bit lines BLe, BLo are connected to node E.

A transistor 141 has a source connected to a corresponding bit line BLe, a drain which is connected to a node providing signal VIRPWR and a gate connected to receive the gate control signal VBLe.

A transistor 142 has a source connected to bit line BLo, a drain which is connected to the node providing signal VIRPWR, and a gate connected to receive the gate control signal VBLo.

The node providing signal VIRPWR is charged at either one of a first or a second supply voltage. Accordingly, transistors 141 and 142 apply the first or second supply voltage to bit lines BLe and BLo, in response to gate control signals VBLe and VBLo.

In addition, an NMOS transistor 143 connects the bit line BLe to node E in response to a BLSHFe signal. An NMOS transistor 144 connects the bit line BLo to node E line in response to a BLSHFo signal.

Page buffer 122 is thus coupled to bit lines BLe, BLo through node E of sense line 125. A PMOS transistor 148 supplies current to the bit lines BLe, BLo via sense line 125 during a read operation. The PMOS transistor 148 is connected between a power supply voltage and the sense line and turns on/off according to a control signal PLOAD.

Importantly, page buffer 122 has two registers 150, 170. The prior art provides only one such register. Both are connected to sense line 125.

Second register 150 is also known as main register 150. Main register 150 includes two NMOS transistors 151, 152, two inverters 153, 154, and a PMOS transistor 155. The data is stored in main latch 156, formed by inverters 153, 154. PMOS transistor 155 forms a precharge circuit for main latch 156.

First register 170 is also called an auxiliary register 170. Auxiliary register 170 includes two NMOS transistors 171, 172, two inverters 173, 174, and a PMOS transistor 175. The data is stored in auxiliary latch 176, formed by inverters 173, 174. PMOS transistor 175 forms a precharge circuit for auxiliary latch 176.

The dual register (made from the two registers 150, 170) of the page buffer 122 of the present invention provides many advantages. Functions are performed better than in the prior art, which are found to justify increasing the magnitude of the page buffer circuit.

Additional structure is provided to facilitate and control exchanging data between the two page buffer registers 150, 170, memory cell array 110, and Y-gating circuit 130.

An NMOS transistor 181 controlled by a control signal PDUMP is turned on to transfer data between auxiliary register 170 and main register 150. Alternately, it is turned off to electrically isolate auxiliary register 170 from main register 150. This transfer is advantageously performed over sense line 125. NMOS transistor 181 is also known as an isolation switch.

NMOS transistors 182, 183 provide for storing information in auxiliary register 170. This is performed responsive to the externally input signals DI and nDI, respectively.

A NMOS transistor 184 connects or disconnects main register 150 to or from a selected one of bit lines BLe, BLo. This is performed when information to be programmed is transferred to the selected one of the bit lines from main register 150.

A NMOS transistor 185 is controlled by a control signal PBDO. Transistor 185 outputs information read out via the selected bit line to the exterior of page buffer 122 during a selected interval of time.

A transistor 186 is prepared for checking the program state, and provides program pass/fail information at a node B of main register 150.

Methods of the invention are now described.

Referring now to FIG. 6, FIG. 7, FIG. 8 and also FIG. 4, programming methods according to the invention are described. Programming is where data is input in the memory cells of a device from outside the device.

In FIG. 6, a flowchart 600 is used to illustrate a programming method according to an embodiment of the invention. The method of flowchart 600 may also be practiced by circuit 100 of FIG. 3.

According to a box 610, first external data is passed through a Y-gating circuit, such as circuit 130. The first external data is passed towards a page buffer, such as page buffer 122. It can be a single datum or many data. It may even be a whole page of data.

According to a next box 620, the first data passed at box 610 is stored at a first register of a page buffer. The first register may be auxiliary register 170.

According to an optional next box 630, a switch may be activated to connect the first register with a second register. The second register may be main register 150. The switch may be NMOS transistor 181, controlled by control signal PDUMP.

According to a next box 640, the first data that is stored in the first register is stored at the second register.

According to an optional next box 650, the switch may be activated to isolate the first register from the second register.

According to a next box 660, the first data that is stored in the second register is stored at a cell of a memory cell array, which is also called programming. Concurrently, second external data is received at the first register, and stored therein. Therefore, an information-storing operation can be carried out without increasing the information-loading time.

In the embodiment of FIG. 3, the concurrent operation of box 660 is made possible because of the isolation of the first register and the second register. Other methods are also possible.

Referring to FIG. 7 and FIG. 8, a programming method of the invention is described in more detail. FIG. 7 shows command signals that may be applied to the circuit of FIG. 5. The horizontal axis is divided into nine time segments, respectively labeled 1, 2, . . . , 9.

FIG. 8 shows how data is transferred in the circuit of FIG. 5, resulting from applying the command signals of FIG. 7. FIG. 8 should be referred to along with FIG. 7, using the same cross-referenced time segments as FIG. 7.

At a first step (time segment 1), a data line 131 is taken to a ground voltage, and transistor 175 is turned on by PBSET signal. This is also known as page buffer setting for the first page.

Afterwards (time segment 2) a node D of auxiliary latch 176 is at a high state, and NMOS transistors 132 and 133 are turned on. Data “0” or “1” in data line is thus stored to auxiliary latch 176 by applying phases of DI and nDI signals. This is also known as data loading of the first page, and loosely corresponds to box 610 described above.

Then (time segment 3), the stored data is transferred to sense line 125 from the auxiliary register 170. This is accomplished by transitioning control signal PDUMP to a logic high state. Prior to transferring the data to main register 150, sense line 125 and node A of latch 156 are precharged by the transistor 148 and 155 respectively.

Afterwards (time segment 4) the signals are zeroed. The process is also called HV enable.

Then (time segment 5), the appropriate one of the bit lines BLe, BLo is set up, by being precharged.

Then (time segments 6 and 7), two actions happen concurrently, corresponding to box 660 above. The data to be programmed is transferred from main register 150 to selected bit line BLe by activating the BLSLT signal, and from there to the memory cell. In addition, the next data to be programmed is stored (loaded) in auxiliary register 170 from the exterior of the memory device.

Generally, the data loading operation is done by byte unit, while programming operation is done by page unit. Data loading means that data is transferred from the data line to the auxiliary register 170, while programming operation means that data transfers from main register 150 to the memory cells in the memory cell array 110. As described above, page unit means that a plurality of memory cells are connected and controlled by a single word line.

Since the two actions take place concurrently, the data-storing characteristic is maintained, even at high volumes of data. Thus implementing the page buffer circuit with auxiliary register 170 is well worth increasing the magnitude of the page buffer circuit.

Then (time segment 8), the read operation is verified, and (time segment 9), the bit lines are precharged again for the next load/program operation.

Referring now to FIG. 9 and FIG. 10, a read operation of the device of FIG. 3 is described in more detail. Data is assumed to be read out from one of the memory cells of array 110, and that gate control signals of memory cells to be read apply appropriate voltages to word lines.

FIG. 9 shows command signals that may be applied to the circuit of FIG. 5. The horizontal axis is divided into six time segments, respectively labeled 1, 2, . . . , 6.

FIG. 10 shows how data is transferred in the circuit of FIG. 5, resulting from the command signals of FIG. 9. FIG. 10 should be referred to along with FIG. 9, using the same cross referenced time segments as FIG. 9.

Briefly, reading out is performed directly through main register 150, bypassing auxiliary register 170. This way, auxiliary register 170 does not obstruct reading data, while it facilitates data loading and data programming as described above.

In order to perform a stable read operation, the bit lines BLe and BLo are first discharged through NMOS transistors 141 and 142 by zeroing the VIRPWR signal, and activating the control signals VBLe and VBLo high. (Time segment 1.) At the same time, a PBRST signal transitions from a logic high state to a logic low state, so that a state of the main register 150 (or an input of inverter 153) is set to a predetermined state (i.e., a logic high state).

Afterwards, the PLOAD signal goes low, and thus PMOS load transistor 148 is turned on. The control signal BLSHFe of the NMOS transistor 143 is made to have a voltage of summing a bit line precharge voltage and a threshold voltage of the NMOS transistor 143. After precharging the bit line BLe with an appropriate voltage, the BLSHFe signal goes to a logic low state of the ground voltage. (Time segment 2.) A precharged voltage of the bit line is varied according to a state of a selected memory cell. For example, in the case where the selected memory cell is an off cell, the precharged voltage of the bit line continues to be maintained. In the case where the selected memory cell is an on cell, the precharged voltage of the bit line is lowered. (Time segment 3.)

If a voltage of the BLSHFe signal is changed into an intermediate voltage between the precharge voltage and the previous BLSHFe signal level, a voltage on sense line 125 is maintained at the power supply voltage by shutting off the NMOS transistor 143 when the selected memory cell is an off cell. If not, however, a voltage on sense line 125 is lowered along a bit line BLe voltage (or is synchronized with a bit line BLe). At a midway point where the BLSHFe signal goes to a logic low state of the ground voltage, the PLOAD signal turns to the power supply voltage.

After this, a gate control signal PBLCHM of NMOS transistor 152 goes to a logic high state of the power supply voltage, and NMOS transistor 151 is turned on or off according to a state of the sense line. As a result, the state of sense line 125 is stored in main register 150. (Time segment 4.)

Then the data stored in main register 150 is transferred to the data line via NMOS transistor 185, which is controlled by control signals PBDO and next via Y-gating circuit 130. (Time segment 6.)

Copy-back methods according to the invention are now described. During the performance of reading operation, it may become necessary to perform a page copy operation by copying data read from a first page of memory cells at a first address to a second page of memory cells at a second address.

Referring now to FIG. 11, a flowchart 1100 is used to illustrate a copy-back method according to an embodiment of the invention. The method of flowchart 1100 may also be practiced by device 100 of FIG. 3.

According to a box 1110, data of a first cell is stored at a first register of a page buffer. This may be performed by reading out data into the auxiliary register 170. Reading out may be performed as described above.

According to a next box 1120, the data stored in the first register is stored at the second register of a page buffer. This may be performed by transferring the read out data between the auxiliary register 170 and the main register 150. The transfer may optionally involve activating a switch to connect the first register with the second register.

According to a next box 1130, the data of the second register is stored at a second cell of the memory cell array. This may be performed as a programming operation, as described above.

Referring now to FIG. 12, FIG. 13, FIG. 14, a copy-back operation of the device of FIG. 3 is described in more detail. Data is assumed to be read out from original memory cells of array 110 into page buffer 122, and copied back there, into different cells.

FIG. 12 shows command signals that may be applied to the circuit of FIG. 5. The horizontal axis is divided into eleven time segments, respectively labeled 1, 2, . . . , 11.

The data is first read out from the cells to the page buffer. It will be recognized that the signal commands in the first four time segments 1, 2, 3, 4 are substantially the same as in those of FIG. 10, except that data is read into auxiliary register 170, instead of main register 150.

Referring to FIG. 13, the data read out into the page buffer is shown. A blank space is also shown, where the prior art of FIG. 2 required an additional indicator bit to indicate the polarity (inverted or not) of the stored data.

Returning to FIG. 12, the data is then transferred from auxiliary register 170 into main register 150 of the page buffer. This takes place during time segments 5, 6.

Then the data is programmed from main register 150 into other cells of the memory, during time segments 7, 8, 9, 10, 11. It will be recognized that the signal commands during time segments 5-11 are substantially the same as in those of FIG. 8.

Referring to FIG. 14, the reprogrammed data is shown. It will be appreciated that the data is stored in the different cells according to the invention without being inverted from how they were stored in the original cells. Accordingly, there is no need to include the indicator bit of FIG. 2, which further saves space.

Erase methods according to the invention are now discussed. Erasing generally dumps data. In a flash memory, the threshold voltage goes to a value between −1V and −3V by applying a high voltage to the memory cells. Data in registers is dumped.

Referring now to FIG. 15, a flowchart 1500 is used to illustrate a verify read operation after erasing according to another embodiment of the invention. The method of flowchart 1500 may also be practiced by device 100 of FIG. 3.

According to a box 1510, data of first memory cell is dumped through a first register of a page buffer.

According to another box 1520, data stored in the first register of the page buffer circuit is dumped through a second register.

According to an optional box 1530, data stored in the first register is checked pass or fail of the memory cell state by transistor 186.

Referring now to FIG. 16 and FIG. 17, an erase method is described for the device of FIG. 3. FIG. 16 shows command signals that may be applied to the circuit of FIG. 5. The horizontal axis is divided into seven time segments, respectively labeled 1, 2, . . . , 7.

FIG. 17 shows how data is erased in the circuit of FIG. 5, resulting from applying the command signals of FIG. 16. FIG. 17 should be referred to along with FIG. 16, using the same cross-referenced time segments as FIG. 16.

In time segments 1 and 2, an erase execution command is received. In time segment 3, bit lines BLe, BLo are grounded for discharge. In time segment 4, a Verify Read operation takes place for a first cell. In time segment 5, a Verify Read operation takes place for a second cell.

In time segment 6, data is dumped through the first register. The data includes data of a memory cell, and also data from main register 150 and supplemental register 170 of the page buffer. In time segment 7, a wired OR operation takes place, and data is dumped from node B of main register 150.

The invention offers the advantage that, even if the size of the page is increased, the program time (or the information-storing time) of the memory is increased slightly or not at all. In addition, a time for loading information on the page buffer circuit is increased in proportion to the increased magnitude of the page.

Referring to FIG. 18, FIG. 19, FIG. 20, FIG. 21, examples are discussed of handling large volumes of data in memories. Efficiencies of the invention are thus illustrated.

FIG. 18 is a depiction of how large volumes of memory are counted for the capacity of a memory device, for two cases, namely A and B.

A three dimensional box depicts the total memory capacity of a device. It can be thought of as a stack of blocks, and each block is a stack of pages. Each page (and also each block) is one byte (1 B) wide. A byte equals eight bits, namely I/O0-I/O7.

In case A, one page is (512+16) 528 B long. Assuming blocks of 32 pages, a capacity of 2048 blocks will yield a device of 264 Mbit.

In case B, enabled by the present invention, one page is (2048+64) 2112 B long. Assuming blocks of sixty-four pages, a capacity of 1024 blocks will yield a device of 1 Gbit.

FIG. 19 displays various design choices for memory devices, including devices A and B of FIG. 18.

FIG. 20 illustrates how a block can be reconfigured to sixty-four pages (such as for device B of FIG. 18) from thirty-two pages (such as for device A of FIG. 18) by designating successive pages of data as “even” and “odd”.

The invention attains faster loading times than the prior art. This is illustrated by examples. Assuming:

T1=11B loading time=0.1 μs

F2=1 page (for two cases of 528 B and 2112 B)

T3=program time=200 μs

F4=1 block (here thirty-two pages)

Then the time required by the device of the prior art for the sequence of data loading, program, data loading, program, etc. requires Total time (prior art)=[(T1×F2)+T3]×F4   Equation (1)

This yields 8,089.6 μs for a device of 528 B and 13158.4 μs for a device of 2112 B. Accordingly, it is not possible to store information of large volume into the page buffer in a short time (the information-storing characteristic deteriorates).

Referring to FIG. 21, data would be loaded and programmed according to the present invention more efficiently. The total time required would be Total time (present invention)=(T1×F2)+(T3×F4)   Equation (2)

This, for a device of 2112 B, yields 6611.2 μs, which is about half of the comparable time of Equation 1. This means that a page buffer circuit of a large volume (e.g., over 2048 B) may now be used.

FIGS. 24 through 29 relate to another embodiment of the invention, to be described in detail below.

FIG. 24 shows a memory cell array 100 in a NAND flash memory device. The memory cell array has a plurality of strings that comprise a plurality of memory cells. Each of the string is connected to one bit line. The strings are connected to a common source line CSL in parallel. The common source line CSL is connected to ground.

In the NAND flash memory device, all of the memory cells that are connected to one word line are simultaneously programmed. In other words, if the word line WL1 is enabled, all of the memory cells MCI are programmed according to the state of the bit line. If the bit line state is “0”, then the memory cells are programmed. If the state of the bit line is “1”, then the memory cells are not programmed.

Afterwards, during the program verify procedure, the state of the memory cells is latched in the data node (N3 of LATCH 2 in FIG. 26).

When the bit line state is “0”, all of the memory cells are not programmed in the first program step.

Normally, the cells are successfully programmed after several steps of the program procedure. Because the coupling ratios of the memory cells are different from one another according to the vagaries of the semiconductor manufacturing process, even though the state of the bit line is a program state “0”, all of the memory cells to be programmed are not necessarily programmed during a single cycle or step of the program procedure. In general, before starting the program procedure, all of the memory cells in a NAND flash memory are erased. Accordingly, all of the memory cells have a negative threshold voltage. After several program steps in the first page, all of the memory cells go to a positive threshold voltage above the verify voltage. In a given page containing plural memory cells, if the first page has finished the first program step then during the program verify procedure all of the memory cells are checked whether the threshold voltage of the memory cells is below the verify voltage or not. The verify voltage is shown in FIG. 25. At that time, even though a portion of the memory cells have been successfully programmed (to “0”), nevertheless most of the memory cells typically are below the range of the verify voltage for the above-described reason.

Referring still to FIG. 24, during the program verify procedure, the voltage level of a common source line CSL rises because of resistors R0, R1, R2, . . . Rm and currents Ic0, Ic1 lc2, . . . Icm. This of course is derived from Ohm's law (V=IR). Those of skill in the art will appreciate that the resistors R0, R1, R2, . . . Rm represent parasitic resistances of the common source line and the currents Ic0, Ic1, Ic2, . . . Icm represent the currents that flow from each bit line to the common source line. Such currents flow through the cells that remain in erased state or that are not sufficiently programmed.

As a result, the voltage level of the common source line CSL rises because of the current flowing through the strings. The fluctuation of the voltage level of the common source is referred to as CSL noise.

This phenomenon occurs more readily after the first program step because of the memory device's condition. But after several program steps, the phenomenon is minimized because the current that flows to the memory cells is minimal.

Referring now to FIG. 25, because of the CSL noise, during the program verify procedure, the LATCH 2 sets the node 3 to a programmed state “1”, even though the threshold voltage of the memory cell is actually below the level of the verify voltage. As a result, the memory cell that is not sufficiently programmed is falsely and misleadingly indicated as a sufficiently (successfully) programmed cell.

For example, if the memory cell MC0 has a threshold voltage of 0.3V after the first program, and the level of the CSL is 0.7V because of the CSL noise, the threshold voltage of the memory cell MC0 becomes 0.7V during the program verify procedure.

If the verify voltage is 0.7V, the memory cell is indicated as a programmed memory cell in the page buffer. Accordingly, the node N3 of the LATCH 2 goes to “1”.

In other words, even though the memory cell (MC0 in FIG. 24) is not sufficiently programmed, the node N3 of the LATCH 2 is in the high state “1”. If the memory cell is programmed in the second step, because the node N3 of the LATCH 2 remains in the state “1”, the threshold voltage of the memory cell MC0 having a 0.3V threshold voltage is not changed.

One object of this invention is to solve this problem.

Another object of this invention is that the memory cell not to be programmed sustains a program inhibit state and the memory cell to be programmed cell is reprogrammed even though the memory cell is falsely indicated as having achieved a programmed state during the program verify procedure.

FIG. 26 depicts the present invention in schematic circuit form. From FIG. 26 it may be seen that the present invention comprises a storing circuit and a restoring circuit not shown in the embodiments of the invention described in parent U.S. application Ser. No. 10/013191.

By reference to FIGS. 26 and 27, the present invention will be explained.

In FIG. 26, a page buffer comprises a first sense amplifier 1, a second sense amplifier 2, a pass/fail check circuit, a storing circuit and a restoring circuit. Those of skill in the art will appreciate that the sense amplifier (1 or 2) is referred to as a register in the parent patent application.

In step F1, the data to be programmed and the data to be program inhibited are loaded to the node N4 in one data register LATCH 1. The data to be programmed is “0” (GND) and the data to be program inhibited is “1” (VDD).

In step F2 (in FIG. 27), the data “0” and “1” are dumped to the node N_DATA. Before step F2, the node N_DATA is pre-charged to VDD level according to a PRE signal.

In step F3, the data in the node N4 is dumped to the node N3 of another data register LATCH2 through the transistor TR12. The phase of the data in the node N3 is the same as the phase of the data in the node N4 and is the inverse phase of the data in the node N_DATA in the storing circuit.

In step F4, the memory cells are programmed according to the state of the node N3 of the other register LATCH2. If the state of the node N3 is “0”, then the memory cell is programmed. If the state of the node N3 is “1”, then the memory cell is not programmed. The program state means that the threshold voltage of the memory goes to a level above the verify voltage, wherein the verify voltage has an intermediate level between the threshold voltage of a programmed memory cell and that of an erased memory cell.

In step F5, the node N3 is restored according to the state of the storing circuit. If the state of the node N_DATA is “1”, then the node N3 is reset to “0”. If the state of the node N_DATA is “0”, then the node N3 retains the previous data.

In step F6, the program verify read procedure is executed. In the first program verify read step, the memory cell that is not sufficiently programmed is indicated as being in a programmed state in the LATCH 2. But the memory cell is indicated as a cell that is not programmed because the CSL noise is reduced after several program steps. Because the node N3 is reset to “0” according to the state of the storing circuit, the memory cell that is insufficiently programmed is programmed during the next program step.

In step F7, the state of the node N3 of LATCH2 is checked in the pass/fail check circuit. If the state of the node N3 is “1”, then the program procedure is finished. If not, then the procedure returns to step F4.

FIG. 28 is a timing diagram of the invented programming and verifying method. The steps F1 through F7 are represented along the horizontal axis, while the various control and data signals are represented along the vertical axis. The control signals include X-Decoder Signals SSL; W/L (Sel.) (selected word line); W/L (Unsel.) (unselected wordline); GSL; CSL (common source line). They also include Page Buffer signals VIRPWR (power supply voltage); VBLe (even bit line voltage); VBLo (odd bit line voltage); BLSHFe (even bit line shift voltage); BLSHFo (odd bit line shift voltage); PBLCHM (gate control); PBLCHC; PLOAD; PBset; PDUMP1; BLSLT (selected bit line); DI (data input); nDI (inverse data input); PRE (precharge); RESET; PDUMP2 and DATA LINE. These signals will be understood in large part to be conventional or understood from the disclosure of the parent application.

As may be seen from FIG. 28, in accordance with the invention, PDUMP2 (during phase F2) precedes PDUMP 1 (during phase F3) so that the previous state of node N3 of LATCH 2 is temporarily stored for restoration of node N3 in the case the bit must be programmed again by returning when needed to step F4, as described above.

Table 1 below illustrates typical voltages for the program and verify modes of programming a memory device of the type described herein. TABLE 1 WL WL BL BL (selected) (unselected) (program) (inhibit) PROGRAM 18 V  12 V   0 V Vcc VERIFY  1 V 4.5 V 0.8 V 0.8 V

The word line voltage step-up, with the programming voltages and steps, proceeds as follows:

-   -   15.5V->VERIFY->16V->VERIFY->16.5V-> . . . (and so on)

In accordance with one embodiment of the invention, the maximum step-up count (number of cycles) is twelve and the step-up voltage increment is 0.5V/step. Those of skill in the art will appreciate that alternative maximum step-up counts and/or alternative step-up voltage increments are contemplated, and are within the spirit and scope of the invention. Typically, programming is completed within in five or six steps so that the maximum count is not reached.

Finally, FIG. 29 is a graph showing the distribution of voltages across a plurality of memory cells after programming in accordance with the invention. It may be seen by contrast to FIG. 25 that, in accordance with the invention, the number of bits successfully programmed rises significantly by effectively pushing the programming of all or substantially all data “0”-programmed cells to a higher threshold voltage that is above their verify voltages. This is illustrated by the lack of any overlap in FIG. 29 of the data “0” programming of all bits (represented by the bell curve on the right side of the graph) and the verify voltage level (represented by a vertical dashed line).

A person skilled in the art will be able to practice the present invention in view of the description present in this document, which is to be taken as a whole. Numerous details have been set forth in order to provide a more thorough understanding of the invention. In other instances, well-known features have not been described in detail in order not to obscure unnecessarily the invention.

While the invention has been disclosed in its preferred embodiments, the specific embodiments as disclosed and illustrated herein are not to be considered in a limiting sense. Indeed, it should be readily apparent to those skilled in the art in view of the present description that the invention may be modified in numerous ways. The inventor regards the subject matter of the invention to include all combinations and sub-combinations of the various elements, features, functions and/or properties disclosed herein.

The following claims define certain combinations and sub-combinations, which are regarded as novel and non-obvious. Additional claims for other combinations and sub-combinations of features, functions, elements and/or properties may be presented in this or a related document. 

1. A semiconductor memory device comprising: a memory cell being set to one of plural threshold voltage; a bit line connected to the memory cell; a first data storage circuit for storing data supplied from an exterior; a read circuit for reading data corresponding to the threshold voltage of the memory cell; a second data storage circuit for storing data read by the read circuit; a first switch circuit connected between the bit line and the first data storage circuit to connect the first data storage circuit to the bit line; and a second switch circuit connected between the bit line and the second data storage circuit to connect the second data storage circuit to the bit line.
 2. The semiconductor memory device according to claim 1, further comprising: a first transistor for setting the first data storage circuit; and a second transistor for setting the second data storage circuit.
 3. The semiconductor memory device according to claim 1, further comprising: a transfer circuit connected to the first data storage circuit for receiving the data.
 4. The semiconductor memory device according to claim 1, wherein the memory cell comprises a non-volatile semiconductor memory cell.
 5. The semiconductor memory device according to claim 1, further comprising: a transistor having a gate and a current path, the gate of the transistor being connected to receive data in the second data storage circuit, one end of the current path of the transistor being supplied with a first voltage, and another end of the current path being supplied with a second voltage.
 6. A semiconductor memory device comprising: a memory cell being set to one of plural threshold voltages; a bit line connected to the memory cell; a first data storage circuit for storing data supplied from an exterior; a read circuit for reading data corresponding to the threshold voltage of the memory cell; a second data storage circuit for storing data read by the read circuit; a first switch circuit connected between the bit line and the first data storage circuit to connect the first data storage circuit to the bit line; and a second switch circuit connected between the bit line and the second data storage circuit to connect the second data storage circuit to the bit line.
 7. The semiconductor memory device according to claim 6, further comprising: a first transistor for setting the first data storage circuit; and a second transistor for setting the second data storage circuit.
 8. The semiconductor memory device according to claim 6, further comprising: a first transfer circuit connected to the first data storage circuit for receiving the data; and a second transfer circuit connected to the first data storage circuit for outputting the data read out from the memory cell to the exterior.
 9. The semiconductor memory device according to claim 6, wherein the memory cell comprises a non-volatile semiconductor memory cell. 